with the processor bus. The VESA Local Bus operates at the speed of the video processor. Several other bus systems have been developed, many of which have not found widespread acceptance in the PC world. Each of these has introduced some technology that is common in the modem bus systems. MICROCHANNEL    ARCHITECTURE (MCA).—  The  MicroChannel  Architecture  (MCA)  bus was developed by IBM in 1987 and increased the bus speed to 10 MHZ. The MCA Bus also introduced the ability  to  configure  the  boards  IRQ  and  DMA  channels through a software configuration program. MCA was the first system to use bus mastering. Bus mastering is a system that allows an intelligent controller board to take control of the bus system for a specified period of time. This allows operations to be completed quickly. Bus mastering differs from DMA in that DMA allows for  direct  transfer  from  a  peripheral  controller  to  RAM, Bus mastering allows for direct transfers between controllers. An example of bus mastering is the ability of a hard drive to transfer graphics directly to the graphics driver, bypassing the CPU and RAM. The major disadvantage of MCA was that it is not compatible with the old ISA standard. Therefore, if you have an MCA machine, the old ISA controller boards will not work. EXTENDED   INDUSTRY   STANDARD ARCHITECTURE.— To compete with MCA, The Extended  Industry  Standard  Architecture  was  (EISA) developed. The EISA Bus included the following features: 32-bit data path 64K of I/O address Capability to address up to 4 giga-bytes of memory Software configuration of boards Bus mastering Unfortunately, the EISA Bus still operates with an 8 MHZ clock, and did not add any additional DMA or interrupt channels. PERIPHERAL  COMPONENT  INTERCON- NECT  (PCI).—  The   Peripheral   Component Interconnect  (PCI)  system  was  designed  to  increase  I/O bus  speeds  while  still  maintaining  compatibility  with previous ISA and EISA boards. A PCI computer has two separate banks of expansion slots, one bank for PCI boards and one bank for the older ISA/EISA boards. The PCI bus uses a “bridge circuit” to isolate the processor bus from the main I/O bus. This bridge circuit  is  designed  so  that  I/O  functions  can  run independently from the CPU. The PCI bus is a 64-bit data bus, but can also support 32-bit computers. This makes the PCI bus useful in both Pentium and 486 systems. The PCI bus can operate a speed up 33 MHZ and also supports bus mastering. Finally,   the   PCI   bus   supports   the Plug-n-Play standard for software configuration of peripheral boards. SUMMARY—CENTRAL  PROCESSING UNITS AND BUSES This  chapter  has  introduced  you  to  central processing units (CPUs) and buses. The following information  summarizes  important  points  you  should have  learned: CENTRAL  PROCESSING  UNITS—  All  the computational operations (logical and arithmetic) and operational decisions are made in the CPU. The CPU controls all computer operations. The CPU has a control section and an arithmetic logic unit (ALU). CONTROL SECTION— The control section directs the sequence of CPU operations, interprets the instructions, and provides the timing and control signals to carry out the instructions. TIMING— Thing in a computer regulates the flow  of  signals  that  control  the  operation  of  the computer.   Computer   operations   rely   on   both synchronous  and  asynchronous  operations.  Timing circuits are used throughout the computer. INSTRUCTION   AND   CONTROL—   The instruction  execution  and  control  portion  of  the  control section includes the combinational and sequential circuits that make up the decision-making and the memory-type  functions.  The  general  process  of execution  of  a  machine  instruction  is  fetch  the instruction, update the program counter or equivalent, translate the instruction, and execute the instruction. INTERRUPTS—   Interrupts are a method of diverting the attention of the computer from whatever process or program it is performing to handle the special condition or event that caused the interrupt signal. Interrupts  allow  the  computer  to  respond  to  high priority demands and still be able to perform normal or lower priority processing. An interrupt is defined as a break in the normal flow of operation of a computer caused by an  interrupt signal.  The break occurs in 5-28