checks parity, and examines a code to determine the
correct sequence. After the sequence is established, the
REI broadcasts the requests and the address to all DMIs
connected to it. The signals on the REI external
interface are expanded to guarantee capture at the DMI
operating synchronously to the REI, which can be
located up to 500 cable-feet away. Once the REI makes
a request, it can send write data if it is performing a write
operation or wait for a response and pass it to the
requestor. The REI responds to the requestor just as
memory does, including faults and aborts (terminates a
process before it is completed).
DIRECT MEMORY INTERFACE (DMI)
BUS. The Direct memory interface is a responder or
slave on the REI bus. The DMI bus is used in some
computers that use an I, O, and IOC bus. The DMI bus
is used to send requests from other enclosures
(computers) to the module (CPU or IOC) requested. It
acts as the requestor and makes requests to the CPU.
When it requests an IOC, it uses IOC read and write
requests. When it requests memory, it uses operand
read or write, instruction read, or replace.
Time Multiplexed Bus
Another variation of the address and data bus is the
time multiplexed bus. This single bus transmits both
addresses and data using a four cycle clock (t1, t2, t3,
and t4). The address is transmitted during the t1 clock
cycle, the direction of data movement is selected during
t2, and the data is transmitted during t3 and t4.
BUS OPERATIONS
The bus control function is performed by a bus
interface unit or logic circuitry similar to it. Control of
a bus line and the proper protocol of requesting a bus
depends on the design of the computer. In computers
with no IOC, the CPU has control of the bus lines. In
computers with an IOC, the CPU will control the
instruction and operand buses and the IOC will control
the memory buses. Bus control is necessary to handle
the large number of bus transactions that take place in
a very short period of time in the computer. There are
basically two factors that must be taken into
consideration in bus communications: transfer
priority and source/destination of the data being
transferred.
Bus transfers are done on a priority basis. The
priorities of bus transfers are determined by the design
of the computers firmware. What part makes the
request is also determined by the design of the
computers firmware; requests may be made by a CPU,
an IOC, and/or a DMI. Examples of priorities that a
computer must deal with include the following (these
examples are not in any type of priority and do not cover
the full range of priorities you may encounter):
Transfers from memory to the CPU, these
transfers move instructions and operands to the
CPU for execution and modification
Transfers from the CPU to memory
Transfers by the I/O in and out of memory
The specific request will identify the source and the
destination of the data. The computers controlling bus
continually and repeatedly checks the bus signal lines
for requests. When it receives a request, it provides the
control signals needed to initiate the transfer. Since
most transfers deal with memory, each transfer consists
of an address exchange and a separate data exchange.
The data will either parallel the address as in a write
operation or move in the opposite direction after the
data has been read from the memory word identified by
the address.
In some computers, the bus systems use holding
registers in both the source and destination sections to
prevent data loss and to help coordinate the data
exchange. In the source logic, the data is placed in a
holding register until it is accepted by the destination
logic. The outputs of the holding register feed the bus
circuitry. In the destination logic, the bus inputs to a
holding register.
After accepting the data, the
destination logic can then move the data from the
holding register to other parts of the logic for
processing.
A variety of command signal names are used to
coordinate the exchange of data on the buses by both
the source and the destination logic. The source logic
generates a ready or signal equivalent when the data is
in the holding register and on the bus. The destination
logic sends an accept or equivalent signal when it has
sensed the ready signal and captured the data on the bus
in its holding register or other logic circuits.
MICROCOMPUTER ARCHITECTURE
AND BUSES
The microcomputer has uses four main types of
buses. These are the
l Processor bus
l Address bus
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