. Buffer control words (BCWs) —Buffer control
words control the type and number of words or bytes
that are to be transferred by the pending operation.
Transfers include 8-bit bytes, 16-bit single words, and
32-bit words.
l Buffer address pointers (BAPs) —Buffer address
pointers specify the next memory address, within the
buffer, for a transfer to take place.
l Chain address pointers (CAPs) —There is one
chain address pointer for each input and output chain of
a channel. Each CAP specifies where in memory the
IOC can find the next chaining instruction.
SERIAL OPERATIONS.— Serial operations are
affected by character size (5 to 8 bits), parity selection
(odd, even, or none), baud rate (50 to 9600 baud), and
synchronous (sync) or asynchronous (async)
interfacing.
Some of the items included in serial
operations are as follows:
. Monitor words —Monitor words are used to
store characters for comparison with received (input)
data characters.
l Suppress word —A suppress word contains a
code that is used to remove specific characters from the
serial transmission stream.
CONTROL MEMORY OPERATIONS.— The
contents of control memory are accessed and modified
through the use of IOC command or chaining
instructions. The exception is actual data transfers in
which the IOC logic updates control memory for each
word or byte transferred. The basic operations that deal
with control memory are the following:
l Initiate transfer (command or chain) —Initiate
transfer loads the input or output BCW and BAP in
control memory for the channel specified and initiates
the input or output transfers.
l Load/write control memory (chain) —
Load/write control memory is used to load or write data
into single control memory word locations.
l Store control memory (command or chain) —
Store control memory is used to write the contents of a
specified control memory address into a memory
address for CPU processing.
l Set/clear flag (chain) —A set/clear flag is used to
set or clear (zero) specified bits or bit groups in control
memory or main memory locations or the channel status
word. It is also used to set or clear the test bit in the
channel status word for conditional jumps.
. Search for sync/set suppress/set monitor
(chain) —The search for sync/set suppress/set monitor
enables or disables sync, monitor, and suppress
capabilities indifferent serial configurations.
* Set/clear discrete (command and chain) —
Set/clear discrete is similar to set/clear flags except that
the set/clear discrete deals with serial interfaces
exclusively. It is used to turn on or turn off specific
serial charnel signals such as data terminal ready.
. Channel control (command or chain) —Channel
control performs a variety of single and multichannel
functions. It can be used to master clear a single or all
IOC channels, input or output. It is also used to enable
or disable all, low priority, or a single
interrupts (external or class III interrupts).
CATEGORIES OF I/O OPERATIONS
channel’s
There are two ways that the I/O section will handle
the transfer of data between the computer and the
external units: direct CPU/external device (direct CPU
interface) communication and direct memory access
(DMA). Each method has it advantages and
disadvantages.
We begin with direct CPU/external
device communication.
Direct CPU Interface
With direct communication, also called
accumulator based I/O, the peripheral devices are tied
directly into the CPU communication bus (control bus,
data bus, and so forth). In a simple I/O scheme, the CPU
handles all I/O transactions by executing one or more
instructions for each word of information transferred.
Three techniques are used: memory mapped I/O, polled
I/O, and interrupt driven I/O.
MEMORY MAPPED I/O.— In memory mapped
I/O, the CPU accesses the I/O device by placing
appropriate addressing information on the bus. The
addressing information uniquely identifies the device
and possibly several addressable locations within the
device. Thus an addressable location in an I/O device
might be treated as a memory location in the computer.
This enables the CPU to transfer data to and from the
I/O device in the same way as main memory transfers.
The following is an example:
7-14
