CONTROL MEMORY
Control memory is a random access memory
(RAM) consisting of addressable storage registers. It is
primarily used in mini and mainframe computers as a
temporary storage for data. Access to control memory
data requires less time than to main memory; this speeds
up CPU operation by reducing the number of memory
references for data storage and retrieval. Access is
performed as part of a control section sequence while
the master clock oscillator is running.
The control memory addresses are divided into two
groups: a task mode and an executive (interrupt) mode.
Addressing words stored in control memory is via the
address select logic for each of the register groups.
There can be up to five register groups in control
memory. These groups select a register for fetching
data for programmed CPU operation or for maintenance
console or equivalent display or storage of data via a
maintenance console or equivalent. During
programmed CPU operations, these registers are
accessed directly by the CPU logic. Data routing
circuits are used by control memory to interconnect the
registers used in control memory.
Some of the registers contained in a control
memory that operate in the task and executive modes
include the following:
Accumulators
Indexes
Monitor clock status indicating registers
Interrupt data registers
CACHE MEMORY
Cache memory is a small, high-speed RAM buffer
located between the CPU and main memory. Cache
memory buffers or holds a copy of the instructions
(instruction cache) or data (operand or data cache)
currently being used by the CPU. The instructions and
data are copies of those in main memory.
Cache memory provides two benefits. One, the
average access time for CPU’s memory requests is
reduced, increasing the CPU’s speed by providing rapid
access to currently used instructions and data. Two, the
CPU’s use of the available memory bandwidth is
reduced. This allows other devices on the system bus
to use the memory without interfering with the CPU.
Therefore, cache memory is used to speed up the flow
of instructions and data into the CPU from main
memory.
This cache function is important because the main
memory cycle time is typically slower than the CPU
clocking rates. To accomplish this rapid data transfer,
cache memories are usually built from the faster
bipolar RAM devices rather than the slower
metal-oxide-semiconductor (MOS) RAM devices.
The RAMs used for cache memory may be either
dynamic RAMs (DRAMs) or static RAMs (SRAMs).
Cache memories are not part of the memory section and
they are transparent to programmers (i.e., not accessible
by machine instruction). Their size varies with the type
of computer; usually they are no more than 64K.
PROPERTIES OF CACHE MEMORY.— All
caches share the following properties:
. A buffered memory or cache memory consists of
a small high-speed memory with main memory
information. This information may be addresses, data,
or instructions. The speed of the small memory is
usually on the order of one magnitude faster than main
memory, and its capacity is typically one or two orders
of magnitude less than main memory.
l A cache memory system requires an identifier
or tag store to indicate which entries of main memory
have been copied into it. Such an area is usually
referred to as the directory or tag store.
l A cache memory requires a logical network and
method of replacing old entries.
. A cache memory uses timing and control.
CACHE PROCESS.— The cache process takes
place when a CPU with a cache initiates a memory
reference. The address of the needed item is generated
and the cache is searched. The method of search
depends on the type of cache mapping used by the
computer system. We can generalize the cache process
into three areas as follows:
l Searches —Reads from the cache directory with
a hit indicating that the data from the requested address
is present, while a miss indicates that the data is not
present.
l Updates —Writes to the cache data as well as to
the directories with new informationo
l Invalidates —Writes only to the directories; this
effectively removes an address that previously resided
in cache.
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