6-35. 6-36. 6-37. 6-38. 6-39. To locate a memory address word, the computer uses which of the following items in memory? 1.   Timing   circuits 2.   Control   circuits 3.   Interface   circuits 4.   Memory   logic The conversion from a logical to a physical memory address is a function of which of the following items in memory? 1.  Memory  logic 2.   Timing   circuits 3.   Control   circuits 4.   Interface   circuits In all computers, for every read operation there will always be a corresponding write operation. 1. True 2. False In order to increase memory speed using interleaving, which of the following items are required? 1.  Memory  modules  of  32  bits 2.  A  minimum  of  8  memory  modules 3.  More  complex  CPU  and  memory control   circuitry 4.  All  of  the  above When odd parity is used for memory fault detection, all words stored in memory will have which of the following bits? 1.  A  logic  1  parity  bit 2.  A  logic  0  parity  bit 3.  An  even  number  of  set  bits  stored  at each  memory  location 4.  An  odd  number  of  set  bits  stored  at each  memory  location 6-40. The memory protection register set is used for which of the following purposes? 1.  To  restrict  read/write  operations  in portions   of   memory 2.  To  protect  memory  from  unplanned power   loss 3.  To  protect  against  erroneous  write instructions 4.  To  limit  access  of  memory  to authorized   users 6-41. In a memory segment within the protected area with all three bits of the memory protection control register set, which of the following operations are allowed? 1.   Execute   protected 2.   Write   protected 3.   Read   protected 4.  All  of  the  above 6-42. Memory lockout is used by larger computers to prevent access to particular areas of memory by task state instructions. Which of the following describes the lockout   function? 1.  It  is  disabled  when  the  CPU  enters  a particular  executive  or  interrupt  state and  enabled  when  the  CPU  enters  the task   state 2.  It  is  enabled  when  the  CPU  enters  a particular  executive  or  interrupt  state and  enabled  when  the  CPU  enters  the task   state 3.  It  is  enabled  when  the  CPU  enters  a particular  executive  ‘or  interrupt  state and  disabled  when  the  CPU  enters  the task   state 4.  It  is  disabled  when  the  CPU  enters  a particular  executive  or  interrupt  state and  disabled  when  the  CPU  enters  the task   state 46