6-7.
6-8.
6-9.
6-10.
6-11.
This bus allows communication between
the CPU and memory or the CPU and the
IOC.
1. C
2. D
3. E
4. F
Controlled by the IOC, this bus responds to
the CPU by using the O bus.
1. E
2. F
3. G
4. H
This bus transmits individual signals to
control and coordinate the operations of the
computer.
1. A
2. B
3. C
4. D
This bus transmits addresses and data by
using clock cycles.
1. E
2. F
3. G
4. H
Acts as a requester, this bus is used to send
requests from other computers.
1. E
2. F
3. G
4. H
6-12.
6-13.
6-14.
6-15.
6-16.
What device accepts requests and uses a
priority network to determine the order in
which it is to respond to the requesters?
1. Operand bus extender
2. REI bus extender
3. CPU
4. DMI
Regardless of whether a computer has an
IOC or not, the CPU will control all buses.
1 . T r ue
2. False
In bus communications, which of the
following factors relating to the data being
transferred must be considered?
1. Source only
2. Destination only
3. Transfer priority only
4. Source, destination, and transfer
priority
Bus requests may be made by all of the
following parts except which one?
1 . C PU
2.
IOC
3. Memory
4.
DMI
Holding registers are used by source and
destination sections to prevent data loss
and to help coordinate data exchange.
1 . T r ue
2. False
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