of an interrupt response by the CPU. Refer to this figure as we describe the process. Terminate  Current  Program  Execution.— Computers  are  not  designed  to  instantly  stop  all  current operations when an interrupt signal is received. They do not halt the current operation until the machine instruction (macro or micro) being processed has been completed.  Interrupt  terminations  effectively  occur between  instructions. There is usually a check for interrupt signals at the end of the current instruction execution   cycle. In  our  example,  an  interrupt  is received during the execution of the third instruction. At  this  time,  the  program  counter  has  been incremented to the next instruction’s address, and all register operations are complete from the execution of the instruction in the instruction register, the third instruction. The program counter reflects the address of the next instruction in the current program and the register contents are stable. It is at this point that the interrupt process will be initiated. Lock Out All Interrupts.— The first event that takes place in interrupt processing is the locking out of all new interrupts. This is done to protect the integrity of  the  process  that  ensures  returning  to  the  same conditions after processing the interrupt. There are a few machine instructions and other processes that must be performed to save the current register data so that it can be restored to the preinterrupt conditions. The interrupt lockout prevents any new interrupts from interrupting this process and potentially losing data or even worse losing track of where the computer was in the interrupted program. Store Program and Register Data.—  Once all interrupts  have  been  locked  out,  the  computer  can  store the current process’s register data in the applicable memory locations. Each class of interrupt is assigned a block of memory locations to store at least the following  register  contents:  program  counter  and  status register(s). The program counter data will allow the interrupted process to be restarted as if the next instruction is being executed  as  in  normal  operation.  The  status  register contents are saved to be able to reinstate the computer’s operational status at the time of the interrupt once the interrupt has been processed. In our example, the data from the three previously executed instructions is stored in memory. The address of the fourth instruction of the current program is also saved. In newer computers, the accumulator, index, and other addressable registers do not require saving since there  is  a  separate  register  set  for  each  task  and executive state. When a new state is entered, the instructions  being  executed  can  only  address  or  modify the registers assigned to that state. Any other task or executive state registers are disabled and their contents are protected until the appropriate state is reentered. Retrieve  Interrupt  Processor  Data.—  After  the register data is saved, the new executive state’s registers are loaded with the interrupt processor program data. The program counter is loaded with the starting address of the processor program (instruction number 1 of the interrupt routine), the status register(s) is/are loaded with  the  operational  status  data  required  by  the program. The interrupt processor data for each class of interrupts is stored in an assigned block of memory cells where it can be retrieved for each interrupt. Enter  Executive  State  and  Enable  Desired Interrupts. — The loading of the status register(s) allows the computer to enter the required executive state and enable the interrupts that can in turn interrupt the interrupt processor. The data bits loaded into the status register(s) effectively change the executive state class (I, II, III, or IV), and enable the active status register set. The  new  status  register  bits  also  set  or  clear interrupt  lockouts  to  enable  or  disable  specific  interrupt classes. The new data in the status register(s) would only enable higher priority interrupts than the interrupt being processed. Execute Interrupt Processor Program.—  The address in the active state’s program counter will now allow for the execution of the interrupt processor program, instruction number 1 of the interrupt routine. The interrupt processor samples the interrupt code words  and  determines  the  appropriate  action  in response to the interrupt. Return to Original Process.—  Upon  completion of the interrupt processor routine, the active state will be switched to the next lower state, either task state or a lower priority executive state, and the program counter and status register(s) for that state will be reloaded with the saved data. The program counter can then call up the next sequential instruction (instruction number 4 of the current program) in the interrupted process and the program will continue as if no interrupt had  occurred.  The  computer  will  normally  return  to  the task  state  program  only  when  all  executive  state procedures have been completed. 5-14