designed so that the odd flip-flops (MT11, MT21, and
so on) are set and cleared by odd phases or lettered
phases and the even flip-flops (MT12, MT22, and so
on) are set and cleared by the even or lettered phases.
The timing chain uses the set and/or clear sides of the
flip-flops to enable and disable circuits throughout the
computer and to generate main timing signals (phases)
such as MT0l or MT02. Main timing signals can be
used to generate other commands, such as starting
arithmetic timing for computers with more
sophisticated mathematical operations.
Main Timing Signals
Main timing signals are used in the CPU to enable
and disable circuits or generate command enables that
are used for control or arithmetic operations. The
majority of data transfers affecting the registers and
associated circuitry in the control section derive their
enables from main timing signals. An example is a
main timing signal used to generate a command enable
such as sending data from one register to another.
Timing sequences are used to issue a series of
commands to perform a particular instruction or
operation. The minimum number of sequences per
instruction or operation is determined by the
requirements of the computer. An example is the
command to enable an instruction sequence, which is
used to acquire the instruction for translation.
Some computers have separate control sections for
each functional area. In that case, each function will
operate independently of the others. That is, a computer
that uses a controller for I/O operations has its own
master clock/main timing chain/main timing signals,
which are independent of the CPUs master clock/main
timing chain/main timing signals.
Sequence Enables and Control
Circuitry to control the sequence enables and to
generate commands depends upon the type of
instruction and method of addressing.
Real-Time Clock (RTC)
The real-time clock (RTC) is used to keep track of
units of real time. The RTC can be loaded, read,
enabled, and disabled by machine instruction. The
register itself is incremented at a rate determined by the
RTC oscillator circuit setting or the external RTC input
The RTC is only incremented when the CPU is
running. It allows the computer, through machine
instructions, to keep track of the passage of time using
readily processed units of time. To prevent register
overflow from causing errors in the timekeeping
process, most RTCs generate register-overflow
interrupts when the register contents increment around
to zero (change from all ONEs to all ZEROs). The RTC
can be enabled and disabled, and updated internally or
The monitor clock register is used to keep track of
time intervals by counting down from its loaded value
to zero. The monitor clock can be loaded, enabled, or
disabled by machine instruction. The monitor clock is
decremented in the same manner as the RTC is
incremented and only when the computer is running.
When the enabled monitor clock reaches zero, a
monitor clock interrupt is generated. A monitor clock
interrupt usually indicates that a designated computer
operation timed out before it was properly completed.
This usually occurs when memory or I/O cannot honor
a request for reasons of priority or hardware failure.
There must be a time limit established to release the
hold on CPU main timing or an indefinite period of
inaction could occur. By using the monitor clock
register to keep track, a time limit is imposed.
Programmable Interval Timers
For those microprocessors that do not have an RTC
or monitor clock registers, there is an additional logic
chip available called a programmable interval timer.
This chip provides up to three counters or count
registers that are software controlled. These registers
can perform the RTC, the monitor clock, or any other
time interval measurements.
The timer communicates with the CPU over the
control and data buses.
The count registers are
independent of each other, addressable (0, 1, or 2), and
can be loaded with count values or have their current
values read and sent to the CPU. These counters are
decrementing or down counters only. They operate off
of separate clock signal inputs so they can be configured
to count at the same or different clock rates. They can
also be programmed to interrupt the CPU when the
count in a selected register reaches zero.