5-18.
In newer computers, a separate register set
for each task and executive state is used,
and these registers are disabled and the
contents protected until the appropriate
state is entered.
1. A
2. B
3. C
4. D
5-19.
The computer enters the required executive
state and enables the interrupts that in turn
interrupt the interrupt processor after the
status registers are loaded.
1. B
2. C
3. D
4. E
5-20.
The new executive state registers are
loaded with the interrupt processor
program data after the register data is
saved.
1.
B
C
2.
3.
D
E
4.
5-21.
The current process’s register data is stored
with at least the contents of the program
counter and status register(s).
1. A
2. B
3. C
4. D
5-22.
5-23.
5-24.
5-25.
5-26.
The first instruction of an interrupt routine
is executed after sampling interrupt code
words.
1. D
2. E
3. F
4. G
The program counter and status register(s)
is/are reloaded with the saved data. The
next instruction, prior to the interrupt
(instruction 4), is called up by the program
counter.
1. D
2. E
3. F
4. G
It requires less time to access control
memory than to access main memory.
1 . T r ue
2. False
Where is cache memory usually located in
a computer?
1. In main memory
2. In the I/O section
3. Between the CPU’s control and ALU
sections
4. Between main memory and the CPU
For rapid data transfers, what two types of
semiconductor devices are usually used by
cache memories?
1. Bipolar DRAMs and MOS SRAMs
2. Bipolar SRAMs and bipolar DRAMs
3. MOS SRAMs and MOS DRAMs
4. MOS DRAMs and bipolar SRAMs
36
